Engineer | MATLAB & Simulink | Quantum Computing | Embedded Systems | FPGA
Member of Engineering Development Group at MathWorks, passionate about multidisciplinary technologies with expertise in MATLAB, Simulink, quantum computing, and embedded systems. Dedicated to creating innovative engineering solutions and empowering the next generation through mentorship.
My journey began in Danthupalli, a small village nestled in the western part of the Godavari river in Andhra Pradesh. Growing up in this humble setting, I completed my primary education from 1st to 5th grade at a state government school right beside my home. The foundation of learning was laid in my mother tongue, Telugu, which remained my medium of instruction through my formative years.
At the age of 11, I walked 3 kilometers daily to attend ZPH School, Aravalli, where I continued my education from 6th to 10th grade. It was here that my academic excellence first shone through—I topped my school and earned an attractive scholarship. This achievement opened my eyes to the transformative power of scholarships and the opportunities they create for underprivileged students like myself.
With guidance from my tuition teacher and the support of a state government scholarship, I took a leap of faith and enrolled in a Diploma in Electronics and Communication Engineering at Smt. B. Seetha Polytechnic, 25 kilometers from home. This marked a pivotal transition—my first experience studying entirely in English. Here, I immersed myself in mathematics, physics, chemistry, engineering drawing, and both theoretical and practical aspects of electronics and communication, discovering my true passion for technology.
Eager to gain industry experience, I joined Medha Servo Drives Pvt Ltd in Hyderabad under the mentorship of Kusuma Garimella. This was my first venture beyond my district and state—a significant step that broadened my horizons. During my time there, I encountered an inspiring colleague who had completed his M.Tech at IISc and joined as an R&D engineer. His journey ignited my dream of pursuing higher studies at the prestigious Indian Institute of Science.
Determined to achieve this goal, I appeared for APECET in 2017, but financial constraints prevented me from pursuing my studies immediately. I continued working for another year, carefully saving money while keeping my academic aspirations alive. In 2018, I successfully cleared APECET again and enrolled at SRKR Engineering College, Bhimavaram—coincidentally, the same town where I had completed my diploma.
My B.Tech journey was supported by the Andhra Pradesh government's fee reimbursement scheme during my third year, which significantly eased my financial burden. Additionally, I received a ₹60,000 scholarship from the North South Foundation, a private organization supporting deserving students. When COVID-19 struck during my final year, I remembered my IISc dream and dedicated myself to GATE preparation, studying 14 hours daily with NPTEL lectures, mock tests, and rigorous problem-solving.
My perseverance paid off when I secured admission to the M.Tech Quantum Technology program at IISc Bangalore. The culture, exposure, and intellectual environment at IISc opened up an entirely new world for me. It expanded my career goals, broadened my ambitions, and connected me with brilliant, like-minded individuals who continue to inspire me. Today, as an Engineer in the Engineering Development Group at MathWorks, I work on cutting-edge quantum computing packages and advanced model-based engineering solutions, contributing to technologies that shape the future.
2021 – 2023
CGPA: 8.6/10
Thesis: Towards measurement of G2 of a microwave frequency single photon source in Circuit QED
2018 – 2021
CGPA: 9/10
2013 – 2016
Rank: Top 1%
2012 – 2013
Rank: 1st in District
2023 – Present
Engineering Development Group
Working on advanced MATLAB and Simulink development, including quantum computing packages and tools. Contributing to cutting-edge model-based engineering solutions and developing innovative features for the MATLAB ecosystem.
Feb 2023 – July 2023
Designed intuitive UI/UX wireframes and prototypes to facilitate seamless student-mentor connections, aligning user flows with the platform's core objective. Developed and deployed the website using HTML, CSS, and SQL, architecting the end-to-end pipeline for user registration, mentor matching, and data management. Integrated social media engagement features and scheduling tools, enabling users to efficiently connect, communicate, and book sessions with mentors of their choice.
April 2022 to July 2022
Worked on digital design projects involving FPGA implementation and verification, gaining hands-on experience with industry-standard tools and methodologies.
Aug 2021 – Feb 2022
Reviewed and improved over 100 pieces of ECE content, ensuring accuracy and clarity. Leveraged technical expertise in electronics and communication engineering to identify and address errors effectively.
2016 – 2018
Successfully transferred technology from R&D to production, demonstrating strong problem-solving and analytical skills in servo drive systems development and implementation.
Feb 2023 - July 2023 | Bangalore, India
During my second year of M.Tech, I founded MentorNow with a vision to motivate students from remote areas and smaller institutions to explore bigger opportunities and reach greater heights. The platform was designed to bridge the gap between aspiring students and quality educational guidance.
Providing comprehensive career guidance, tutoring, and personalized support from class 6 to undergraduate level, empowering students to excel academically and in competitive exams through experienced mentors specializing in Mathematics, Physics, Engineering, Biology, and more.
Note: After a few days, I handed the MentorNow operations to a startup MentiMeet for which I developed the website. For MentorNow, I connected with all the students for their feedback and improvements.
AIR 219
2022
Graduate Aptitude Test in Engineering
AIR 695
2021
Graduate Aptitude Test in Engineering
Rank 205
2018
Andhra Pradesh Engineering Common Entrance Test
Rank 405
2017
Andhra Pradesh Engineering Common Entrance Test
In this academic project, I developed a complete FPGA-based system for measuring the second-order correlation function G²(τ) to investigate photon antibunching in circuit QED experiments. The firmware, written in Verilog and modeled in SystemC, implements the correlation algorithm for positive lags by sequentially shifting input sequences and accumulating results using a modular architecture comprising memory, state machine controller, MAC (multiply-and-accumulate) unit with booth multiplier and carry-select adder, correlator, and magnitude square modules. The top module integrates all components and manages data flow and synchronization, while counters and register delays ensure precise timing and control. Comprehensive test benches were created for each module and the integrated system, using both direct and CORDIC-generated data to verify functionality and performance prior to hardware deployment. Python scripts were developed to automate experiment control, data acquisition from the FPGA, and post-processing, including statistical analysis and visualization of G²(τ) to reveal photon antibunching. This project resulted in a robust, real-time measurement platform that enabled detailed characterization of quantum optical phenomena in circuit QED systems, demonstrating seamless integration of hardware, firmware, and software for advanced quantum measurements.
Developed a Python framework to analyze charge stability in Double Quantum Dot systems, modeling electrostatic energies and visualizing stability regions with heatmaps in a reproducible Jupyter Notebook.
Built a project using Grover's algorithm to solve the graph coloring problem, including a custom oracle for color assignment validation and flexible querying for valid colorings. Demonstrated combinatorial optimization via quantum circuits and visualization.
In this project, I designed, simulated, and analyzed an 8-bit ripple carry adder optimized for minimum area while maintaining acceptable performance in terms of delay and power. The architecture was chosen based on the moderate bit-width and the goal of minimizing transistor count. For the 1-bit full adder, we explored various logic styles and finalized a 12-transistor design utilizing two XNOR gates (built with pseudo-NMOS and pass transistor logic) and a 2-to-1 multiplexer (comprising a CMOS inverter and two transmission gates) to achieve rail-to-rail carry logic. The complete 8-bit adder was constructed by cascading these 1-bit modules. The design was implemented and verified at the transistor level using LTSPICE, with all circuits operating at a supply voltage of 1V. Detailed schematics and simulation waveforms were generated for the 1-bit adder, XNOR gate, and 2-to-1 MUX. The final 1-bit adder occupied an area of 48,600 nm², leading to a total area of 0.39 μm² for the 8-bit adder. The worst-case delay and power were measured as 630 ps and 260 μW, respectively, using specific input transition patterns and LTSPICE measurement commands. This project demonstrates a practical approach to low-area, efficient digital adder design using advanced logic techniques.
Designed and implemented an IoT-based road safety solution for hilly regions, integrating image processing and OCR for automatic number plate recognition to log vehicle entry and exit times to the cloud. Developed sensor-driven modules to detect traffic violations such as overspeeding, issuing real-time warnings to drivers. If violations persisted, the system automatically recorded the event with the associated number plate and transmitted the data to authorities via GSM, enabling proactive roadway blocking for repeat offenders. This project enhanced both traffic monitoring and enforcement, improving safety and traffic flow in challenging terrains.
In this project, I explored the theoretical and practical aspects of collision finding in cryptographic hash functions, focusing on the security implications for schemes like SHA-256. The work involved a comprehensive study of both classical and quantum algorithms for finding hash collisions, with particular attention to the Brassard–Høyer–Tapp (BHT) quantum algorithm and its resource complexity compared to classical methods. I analyzed the mathematical foundations of collision resistance, implemented and evaluated classical approaches such as table lookup, parallelization, and the rho method, and compared their efficiency to quantum strategies including Simon's and Grover's algorithms. Through detailed analysis, I demonstrated that certain non-quantum algorithms, notably the rho method, outperform the BHT quantum algorithm in both time and hardware cost, challenging claims of quantum advantage in this context. The project included rigorous probability analysis, complexity calculations, and critical review of recent research, ultimately concluding that quantum algorithms do not currently offer a practical improvement over the best classical collision-finding methods for cryptographic hash functions.
Finite state machine implemented in two modes - manual and automatic - to make the inverted pendulum stand in stable position using advanced control theory and real-time feedback mechanisms.
Designed and implemented a restoring divider for unsigned 8-bit integers on the BASYS3 FPGA board. Developed Verilog modules for division with user input via slide switches and output on 7-segment LEDs, enabling straightforward hardware deployment.
Developed a sine and cosine waveform generator using the CORDIC algorithm on the BASYS3 FPGA, with a three-stage pipelined and look-up table architecture in Verilog. Integrated output with Pmod DAC2 for analog signal conversion and oscilloscope visualization, achieving signal generation.
I'm always open to discussing new opportunities, collaborations, or just having a chat about quantum computing, embedded systems, or any exciting tech projects.